An MTJ element used for a memory cell of an MRAM includes a fixed magnetic layer, a free magnetic layer, and a tunnel insulating film. In the fixed magnetic layer, the direction of the magnetization is fixed to an arbitrary direction. In the free magnetic layer, the direction of the magnetization is changeable by an external magnetic field. The tunnel insulating film is sandwiched between these two magnetic layers. In the MRAM, one-bit storage information is allocated to the relative magnetization state between the fixed magnetic layer and the free magnetic layer. For example, in the case where the magnetization of the fixed magnetic layer and the magnetization of the free magnetic layer are directed to the same direction, i.e., in the case of the parallel state, the magnetization state is defined as “0”. In the case where the magnetization of the fixed magnetic layer and the magnetization of the free magnetic layer have directions different from each other by 180 degrees, i.e., in the case of the antiparallel state, the magnetization state is defined as “1”. Further, a read operation of the MRAM is implemented by using the fact that the resistance value of the MTJ element varies depending on the above-mentioned magnetization state. FIG. 1 is a schematic diagram illustrating a typical write principle of the MRAM. A write current ix is flowed through a write word line extending parallel to the easy magnetization axis of a magnetic layer, and a write current Iy is flowed through a write bit line extending perpendicular to the easy magnetization axis. As a result, a synthetic magnetic field generated by these write currents reverses the magnetization of the free magnetic layer (cell A). As described, the magnetization reversal characteristics of the MTJ element are used to select a memory cell and to perform a write operation. FIG. 2 is a graph illustrating a relationship between the write currents and the write margin. The vertical axis and the horizontal axis represent the write current Ix and write current Iy, respectively. The write current has an upper limit and a lower limit (in the diagram, indicated as the “operational margin”). The write margin is narrow. For this reason, in order to selectively perform writing into the selected memory cell (cell A), it is necessary to accurately control the current value and the current waveform. This complicates the current source circuit, and make it difficult to perform a high-speed write operation at 100 MHz or more.
A memory cell (2-Transistor-1-MTJ element type memory cell: 2T1MTJ cell) in which a write current is electrically selected with a transistor or a diode is disclosed in Japanese Laid-Open Patent Application No. JP-A 2004-348934 (US 2004/100835A1). FIG. 3 is a schematic diagram illustrating the configuration of the 2T1MTJ cell in this conventional technique. As illustrated in FIG. 3, the 2T1MTJ cell includes: a transistor 111 connecting a bit line BL with a write line 115; a transistor 112 connecting a bit line /BL with the write line 115; and an MTJ element 113 directly placed on the write line 115. In a write operation, the word line WL associated with the selected memory cell is activated to place the transistors 111 and 112 into the ON state. This causes a write current Iw flowing through the bit lines BL and /BL to flow through the write line 115. At this time, the magnetization of the MTJ element 113 is reversed by a write magnetic field Hw generated by the write current Iw. It should be noted that the bit lines BL and /BL are formed in an interconnection layer sufficiently distant from the MTJ element 113 such that the magnetic field generated by the write current not flowing through the write line 115 but flowing only through the bit lines BL and /BL does not reverse the magnetization of the MTJ element 113. For example, in the case where the MTJ element 113 is formed between a third layer interconnection and a fourth layer interconnection, a first layer interconnection may be used for the bit lines. As described, one feature is that a memory cell in a non-selection state is not supplied with the write magnetic field Hw to eliminate the half-selection state. Accordingly, the writing method using the 2T1MTJ cell dramatically improves the selectivity of the memory cells in writing, and also eliminates the need for accurately controlling the write current value or the current waveform. Accordingly, the write circuit can be simplified with the use of a logic circuit like a decoder of an SRAM, and therefore a high-speed write operation at a GHz level can be achieved.
As described above, the 2T1MTJ cell achieves a high-speed write operation as an SRAM, as compared with a write method used in a conventional MRAM. However, a same read method as in the conventional MRAM is used, and therefore the operation speed of the 2T1MTJ cell is limited by the read speed.
FIG. 4 is a circuit block diagram illustrating a basic configuration of an MRAM 101 using the 2T1MTJ cell. A memory array 102 includes cell columns in which the 2T1MTJ cells C (also simply referred to as cells) are arranged in a matrix form, and reference cell columns in which two columns of reference cells R are arranged.
In a write operation, a row decoder 103 selects a selection word line WL from a plurality of word lines WL. A column decoder 104 selects at least one pair of selection bit lines BL and /BL from a plurality of bit lines BL with switches 106. That is, by the selection word line WL and selection bit lines BL and /BL, at least one selection cell C into which data is to be written is selected from the plurality of memory cells C. The selection cell C is electrically connected to the column decoder 104 with the switch 106. Then, a write current Iw from a write current circuit (not shown) is flowed through a path from the column decoder 104 to the selection bit line BL, to the write line 115 of selection cell C, to the selection bit line /BL and to the column decoder 104.
In reading, on the other hand, the row decoder 103 selects a selection word line WL from the plurality of word lines WL. The column decoder 104 selects a selection bit line BL from the plurality of bit lines BL with switches 107. That is, by the selection word line WL and the selection bit line BL, a selection cell C from which stored data is to be read is selected from the plurality of memory cells C. The selection cell C is electrically connected to one of input terminals of a sense amplifier 105 with the switch 107. A sense current IR to flow through an MTJ element 113 of the selection cell C is generated, and supplied to the one input terminal of the sense amplifier 105.
At the same time, the column decoder 104 continuously places two reference bit lines BLR0 and BLR1 into the selected state with the switches 107. That is, by the selection word line WL and two reference bit lines BLR0 and BLR1, selection reference cells R0 and R1 are simultaneously selected from a plurality of reference cells R0 respectively stored with data “0” and a plurality of reference cells R1 respectively stored with data “1”. The selection reference cells R0 and R1 are electrically connected to the other input terminal of the sense amplifier 105 with the switches 107. A reference current Iref (0) flowing through an MTJ element of the reference cell R0, and Iref (1) flowing through an MTJ element of the reference cell R1 are averaged to thereby generate a reference voltage Vref used as a read criterion, which is supplied to the other input terminal of the sense amplifier 105.
That is, the one of the two input terminals of the sense amplifier 105 is connected with the selection cell C, and the other input terminal is connected with the selection reference cells R0 and R1. Therefore, load capacitances of the two input terminals of the sense amplifier are not the same. Accordingly, the speed at which a sense signal (the sense current IR0 flowing through the selection cell C) is settled, and the speed at which the reference signal (the reference currents Iref flowing through the reference cells) is settled are different. Accordingly, the identification operation of the sense amplifier 105 cannot be performed before the sense signal and the reference signals are sufficiently settled, and therefore the read speed is limited. Also, the variations in the power supply voltage, and the influence of capacitance coupling between interconnections are not constant, and therefore this technique is disadvantageous also in terms of the noise tolerance. Accordingly, it is not easy to increase the read speed of the MRAM using the 2T1MTJ cell. As a result, the operation speed of the MRAM, i.e., the random access time is limited by the read time of 10 ns or more.
A configuration of an MRAM to achieve a high-speed read operation is disclosed in Japanese Laid-Open Patent Application No. JP-A 2002-197852 (U.S. Pat. No. 6,349,054 B1). According to this document, memory cells in even-numbered rows connected to bit lines BL, and memory cells in odd-numbered rows connected to bit lines /BLs constitute a memory array. Dummy cells (equivalent to the above-described reference cells) used for the read criterion are also provided for each of the even-numbered and odd-numbered rows. The dummy cell retains a resistance value that is an intermediate between the resistance value Rlow corresponding to data “0” and the resistance value Rhigh corresponding to data “1”. Also, in the case where a memory cell in an even-numbered row is selected, a dummy cell in an odd-numbered row is used, whereas in the case where a memory cell in an odd-numbered row is selected, a dummy cell in an even-numbered row is used. According to this technique, load capacitances of the bit lines BL and /BL are adjusted to be equal to each other, and therefore the read time is improved. However, the same writing method as in the conventional MRAM illustrated in FIG. 1 is used, and therefore the operation speed in this technique, i.e., the random access time is limited by a write time of 10 ns or more. Also, the cell area is increased as compared with the case where memory cells are arranged in a matrix form.
As described above, it is not easy to increase the operation speed (random access time) of the MRAM as that of the SRAM. When the 2T1MTJ cell described in Japanese Laid-Open Patent Application No. JP-A 2004-348934 is used to configure a memory array based on the idea described in Japanese Laid-Open Patent Application No. JP-A 2002-197852, for example, the cell area is increased to approximately 2 times, which is impractical. There is a need for a high-speed semiconductor storage device using a magnetoresistance effect element (e.g., MRAM). There is also a need for a semiconductor storage device using the 2T1MTJ cell (e.g., MRAM), which can achieve a high-speed read operation without cell area overhead, and achieve a high-speed write operation.
As a related technique, a semiconductor device is disclosed in Japanese Laid-Open Patent Application No. JP-A 2000-12790. In this semiconductor device, in which a memory cell array in a memory section of the semiconductor device is divided into a plurality of regions and an even number of I/O lines are assigned and arranged into the divided memory cell array regions, the memory section is designed to provide a predetermined bit configuration. In the bit configuration of the memory section, the basic unit may be nine bits. Among the even number of the I/O lines, two I/O lines respectively assigned to adjacent memory cell array regions may be collected in a single I/O line, and the bit number in the bit configuration of the memory cell section may be made half of the bit number in the predetermined bit configuration.
Japanese Laid-Open Patent Application No. JP-A 2003-281880 (U.S. Pat. No. 6,822,897 B2) discloses a thin film magnetic storage device. The thin film magnetic storage device includes a plurality of memory cells, a plurality of data lines, and pluralities of first and second gate lines. The plurality of memory cells are arranged in rows and columns along first and second directions, and a first group is defined for each group of memory cells adjacent to each other along the first direction, whereas a second group is defined for each group of memory cells adjacent to each other along the second direction. Each of the plurality of data lines is provided along the first direction for each of the first groups. The plurality of first and second gate lines are provided along the second direction, and each of them is provided for each of the second groups. Each of the memory cells includes: a magnetoresistance element having a variable electrical resistance depending on magnetically written storage data; and an access transistor for electrically connecting the magnetoresistance element between the associated data line and a fixed voltage in data reading. Each of the access transistors is turned on and off depending on the voltage of a predetermined one of the associated first and second gate lines, which is predetermined for each of the first groups.
Japanese Laid-Open Patent Application No. JP-A 2003-346474 (U.S. Pat. No. 6,618,317B1) discloses a thin film magnetic storage device. The thin film magnetic storage device includes a memory array, a plurality of bit lines, a plurality of column selection lines, an address decoder, and first and second write control circuits. In the memory array, a plurality of memory cells each storing magnetically written data are arranged in a matrix form. The plurality of bit lines are provided for a plurality of memory cell columns, respectively. The plurality of column selection lines are provided for the plurality of memory cell columns, respectively. Upon data writing, the address decoder sets voltages of the plurality of column selection lines in accordance with the column selection result. The first and second write control circuits are provided for one-side ends and the other-side ends of the plurality of bit lines, respectively, and supply to a selected bit line data write currents having a direction depending on write data in the data writing. The first write control circuit includes: a first driver for, in the data writing, electrically connecting between one of first and second voltages, which depends on the write data, and a first shared node; and a plurality of first switch circuits each of which is provided between the one-side ends of the plurality of bit lines and the first shared node, and turned on depending on the voltage level of corresponding one of the plurality of column selection lines. The second write control circuit includes: a second driver for, in the data writing, electrically connecting between the other one of the first and second voltages, which depends on the write data, and a second shared node; and a plurality of second switch circuits each of which is provided between the other-side ends of the plurality of bit lines and the second shared node, and turned on depending on the voltage level of corresponding one of the plurality of column selection lines.